NXP Semiconductors /MIMXRT1064 /TSC /DEBUG_MODE

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Interpret as DEBUG_MODE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADC_CONV_VALUE0 (ADC_COCO)ADC_COCO 0EXT_HWTS0 (TRIGGER_0)TRIGGER 0 (ADC_COCO_CLEAR_0)ADC_COCO_CLEAR 0 (ADC_COCO_CLEAR_DISABLE_0)ADC_COCO_CLEAR_DISABLE 0 (DEBUG_EN_0)DEBUG_EN

TRIGGER=TRIGGER_0, ADC_COCO_CLEAR=ADC_COCO_CLEAR_0, DEBUG_EN=DEBUG_EN_0, ADC_COCO_CLEAR_DISABLE=ADC_COCO_CLEAR_DISABLE_0

Description

no description available

Fields

ADC_CONV_VALUE

ADC Conversion Value

ADC_COCO

ADC COCO Signal

EXT_HWTS

Hardware Trigger Select Signal

TRIGGER

Trigger

0 (TRIGGER_0): No hardware trigger signal

1 (TRIGGER_1): Hardware trigger signal, the signal must last at least 1 ips clock period

ADC_COCO_CLEAR

ADC Coco Clear

0 (ADC_COCO_CLEAR_0): No ADC COCO clear

1 (ADC_COCO_CLEAR_1): Set ADC COCO clear

ADC_COCO_CLEAR_DISABLE

ADC COCO Clear Disable

0 (ADC_COCO_CLEAR_DISABLE_0): Allow TSC hardware generates ADC COCO clear

1 (ADC_COCO_CLEAR_DISABLE_1): Prevent TSC from generate ADC COCO clear signal

DEBUG_EN

Debug Enable

0 (DEBUG_EN_0): Enable debug mode

1 (DEBUG_EN_1): Disable debug mode

Links

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